The present invention generally relates to packaging for a semiconductor chip and is particularly directed to providing a chip scale package for a chip. In certain embodiments, the invention relates to a packaging system that blocks encapsulant from flowing beyond areas intended to be encapsulated. The invention is particularly well suited for encapsulating connections formed between chip bonding pads and leads on a flexible substrate in a chip scale package.
After a chip is fabricated on a wafer and separated therefrom, it is packaged for protection and to facilitate its integration into a circuit on a printed circuit board (xe2x80x9cPCBxe2x80x9d), flexible printed circuit (xe2x80x9cFPCxe2x80x9d), or other board or electronic product (hereinafter such products are collectively referred to as xe2x80x9ccircuitry productsxe2x80x9d). The package also provides the chip (1) a lead system for connecting the chip to a PCB or other product; (2) physical protection; (3) environmental protection; and (3) a mechanism for heat dissipation. A package typically includes an enclosure or body, which may also be referred to herein as an xe2x80x9cinterposer.xe2x80x9d Enclosures may be made of ceramic, epoxy, and flexible substrates based on polyimide, for example. The enclosure also includes an inner lead system for electrically connecting to bonding pads on the chip and an outer lead system for electrically connecting the packaged chip to a circuitry product. Conductive traces may also be included between inner and outer lead systems.
Numerous packaging techniques exist. Generally, each involves putting the chip into an individual package, which can be connected directly to a circuit board; putting the chip into a multichip module (xe2x80x9cMCMxe2x80x9d) with other chips that are packaged together; or using direct chip attachment (xe2x80x9cDCAxe2x80x9d) to connect the chip to a circuitry product.
The chip may be electrically connected to the inner lead system of the package via bonding wires, solder balls, or other chip connectors bonded to the bonding pads of the chip. Typically, the chip""s bonding pads are in an array along outer edges of the chip. However, as discussed in more detail below, a chip may have its bonding pads arrayed off the edges, for example, in the center of the chip.
The bonds formed between the chip bonding pads and the package lead system is typically covered or filled with an encapsulant to protect the bonds from physical and environmental damage and to preserve their function. In one conventional method suitable for use with chips having bonding pads at edges, chips are mounted upside down (circuitry side down) on a coverlay tape to encapsulate the non-circuitry side of the chip. In this process, the encapsulant flows along the tape and the chip to fill in the space left between the die and the substrate. The encapsulant is cured and the tape removed. One problem with this approach is containing the encapsulant in intended regions of application on the chip. However, liquid encapsulants pose certain problems. If the liquid is formulated too thick, it can leave voids after it solidifies. Interconnections that are covered by encapsulant having voids may not be protected adequately and may be adversely affected electrically. If encapsulant liquid is formulated too thin, it can flow beyond intended areas of the chip and interposer. Due to overflow of the encapsulant, the excess encapsulant must be trimmed off the chips. Thus to make an even-edged package, labor, time and cost are added to the packaging process.
Various forms of packaging have evolved based on the foregoing packaging fundamentals, including plastic ball grid array package (PBGA) and direct chip attach (xe2x80x9cDCAxe2x80x9d). Unfortunately, these and other conventional packaging techniques suffer from disadvantages. These disadvantages include excessive package size, weight, and cost. The packages may also require excessive process steps and additional equipment. These disadvantages have become particularly heightened as advancements have been made in wafer processing and chip fabrication. Packaging technology, at least initially, did not keep pace with such advances.
In reaction to the need for packaging advancements that are suitable for use with more advanced, higher density chips, the industry has developed a packaging technology called chip scale package (xe2x80x9cCSPxe2x80x9d). The objectives of CSP include providing a package that avoids adding size and bulk to the chip to maintain the profile of the chip. A package area that is less than 1.2 times the chip area is generally considered a CSP. See LAU et al, CHIP SCALE PACKAGE: DESIGN MATERIALS, PROCESS, RELIABILITY, AND APPLICATIONS (McGraw-Hill 1999), p.2. There are at least three significant advantages to employing CSP technology: higher component density, more efficient assembly automation, and enhanced product performance.
There are at least 40 types of CSP technology, some being close variations of others. Representative technologies are described in LAU et al, supra. One popular CSP technology uses a thin flexible substrate (interposer), which may be used in a process called xe2x80x9ctape automated bondingxe2x80x9d (TAB). TAB is particularly useful where extreme package thinness needed. In TAB bonding, an electrical lead system is formed on a thin flexible, tape-like substrate. The lead system may be formed by a patterning process similar to that used in wafer fabrication or by mechanically stamping or chemically bonding the conductive materials of the lead system on to the substrate. The resulting tape appears similar to a camera or movie film, with multiple sets of lead systems spaced along the length of the tape. Tape is provided in reels or frames for use in the packaging process. Like camera or movie film, the tape may have sprocket holes for a sprocketed tape feeder to move the tape over a chip held in a chuck or die mounter. The tape is moved until a lead system aligns with a bonding pad array on a chip. After alignment, the leads are connected to the bonding pads thermosonically with a tool called a thermode or thermosonic bonder. The thermode has a surface that is heated and moved down upon the leads on the tape. The thermode presses the leads downwardly onto the bonding pad array. The heat and pressure of the thermode bond the leads to the pads. After attachment, bonds are covered with encapsulant using a coverlay tape.
One of the better known CSP""s using a flexible package is the xcexc-BGA(copyright) flexible interposer of Tessera, in San Jose Calif. The xcexc-BGA(copyright) interposer has ribbon-like flexible leads for chip level interconnection and a compliant elastomer between the interposer and the chip to relieve stress in the connections arising from the connected structures having different thermal expansion properties. Thermosonic bonding is used to bond the leads on the interposer to the chip""s bonding pads.
One advantage of xcexc-BGA(copyright) interposer and similar flexible interposers is that the bonding areas are not restricted to the outer edges of the chip. Thus, a flexible interposer is particularly useful in bonding chips having an array of bonding pads disposed along a central axis of the chip. Therefore, flexible interposers, such as the xcexc-BGA(copyright), are quite suitable for chips with center bond pads. Most DRAM chips above 16 MB fall into this category.
In many CSP processes, including TAB processes, a liquid encapsulant is applied over interconnections to protect them. The general problems of using encapsulant are applicable to CSP processes.
The encapsulation process poses significant drawbacks relative to flexible interposers for chips with center bond pads. In center bonded packages, the tape interposer overlies the entire surface of the chip, except for an opening in the interposer over the array of bond pads. After leads such as conductive ribbons or other interconnects are pressed down on the bond pads and bonded thereto, the bonds must be encapsulated. After bonding, liquid encapsulant is applied over the interconnections in a cavity defined by a floor of the top surface of the chip and sidewalls of the parallel rows of interconnections and elastomer material interposed between individual interconnects. In such chips, at the opposite ends of the parallel rows of interconnections there is an open passage. The passage results from a gap in assembled material. For example, this passage may be defined by the floor of the top surface of the chip, a ceiling of the downward surface of the tape, and sidewalls of an elastomer material interposed between the floor and ceiling. When encapsulant is applied over the interconnections, the passage is a flow path for encapsulant to places not intended to have encapsulant. This can cause significant problems. For example, if encapsulant flows through a passage beyond the edges of the chip/interposer, then trimming and cleaning of the encapsulant is required. In extreme cases, the packaged chip may even have to be discarded.
Unfortunately, the problem of such encapsulant overflow has not been easily solved. Fashioning the elastomer material interposed between the chip and interposer tape is difficult and has limitations. Therefore, it has not been possible to extend this material so that there is no passage left after the chip is attached to the interposer with elastomer.
For the foregoing reasons, there is a significant need for a solution to the problems of encapsulant overflow. The following portions of this specification describe how the invention disclosed and claimed herein elegantly and efficiently provides a solution to the problem associated with encapsulation overflow.
The present invention overcomes the problems associated with the prior art by providing a packaged chip and a process for making the packaged chip that eliminates previously needed materials, equipment, and steps for encapsulating chip/package interconnects. The invention is particularly advantageous for encapsulating a center-bonded chip, eliminating the need for a coverlay tape in the encapsulation process.
The present invention also relates to an interposer that includes a dam portion that extends across the flow path of encapsulant, so that the encapsulant does not flow over undesired areas on the die. The present invention further relates to a method for making an interposer with a built-in encapsulant dam.
In one novel embodiment, the present invention provides a packaged chip comprising: a chip having one or more bonding pads disposed away from or off the edges of the chip; an interposer attached to the chip, the interposer having one or more leads interconnected to the one or more bonding pads, at least a portion of the interconnections between leads and bonding pads being covered by an encapsulant; and at least one dam disposed between the chip and interposer and blocking an encapsulant flow path in the package.
In another novel embodiment, the present invention provides a method of forming a packaged chip comprising: providing a chip having one or more bonding pads disposed off the edges of the chip; attaching the chip to an interposer, the interposer having one or more leads for bonding to the bonding pads; interconnecting the leads to the bonding pads to form an interconnection region; placing a dam across an encapsulant flow path in the package being formed; and introducing an encapsulant to at least a portion of the interconnection region.
In another novel embodiment, the present invention provides a method of forming a packaged chip comprising: providing a chip having one or more bonding pads disposed off the edges of the chip; attaching the chip to an interposer comprising a flexible substrate, the interposer having one or more leads for bonding to the bonding pads; interconnecting the leads to the bonding pads to form an interconnection region; placing a dam disposed on the interposer across an encapsulant flow path in the package being formed; and introducing an encapsulant to at least a portion of the interconnection region.
In another novel embodiment, the present invention provides an interposer for attachment to a chip, comprising: a substrate having one or more conductive traces for making electrical connections with bonding pads on a chip; and a dam disposed on the interposer for blocking an encapsulant flow path in a structure resulting from a combination of the interposer with a chip.
In another novel embodiment, the present invention provides an interposer for attachment to a chip, comprising: a flexible substrate having one or more conductive traces electrically connected to one or more leads for interconnecting with bonding pads on a chip, one or more of the leads being off the edge of the interposer for interconnecting with bonding pads off an edge of the chip; and a dam disposed on the interposer for blocking an encapsulant flow path in a structure resulting from a combination of the interposer with a chip, the dam comprising a deflectable structure on the interposer.
In another novel embodiment, the present invention provides a method of forming an interposer for attachment to a chip, comprising: providing a flexible substrate; forming on the substrate conductive traces terminating in a plurality of leads for making electrical connections with bonding pads on a chip; and forming a dam on the interposer for blocking an encapsulant flow path in a structure resulting from an assembly of the interposer with a chip.
In another novel embodiment, the present invention provides a method of forming an interposer for attachment to a chip, comprising: providing a flexible substrate; forming one or more conductive traces on the substrate; forming one or more leads electrically connected to traces for interconnecting with bonding pads on a chip, one or more of the leads being off the edge of the interposer for interconnecting with bonding pads off an edge of the chip; and forming a dam disposed on the interposer for blocking an encapsulant flow path in a structure resulting from a combination of the interposer with a chip, the dam comprising a deflectable structure on the interposer.
The foregoing novel embodiments may include other advantageous features, defining further novel embodiments. Some such features are noted below and may be added to one or more of the foregoing embodiments alone or in combinations. In this regard, the chip may include bonding pads disposed substantially along a central axis with leads from the interposer interconnected thereto so that the package comprises a center bonded package, the package having an encapsulant covering the interconnections, the package having a flow path at at least one end of the centrally disposed interconnections, the flow path being blocked by a dam.
The packaged chip may be designed also to have a dam at each end of the centrally disposed interconnections, each flow path being blocked by a dam. The dam may be disposed on the interposer. The dam may be a structure formed on the surface of the substrate in the package, such as the interposer, the structure being deflectable so as to be positionable across an encapsulant flow path in the package. The dam may be a real or dummy lead on the interposer. The dams may be formed in a process for patterning or stamping conductive material onto the surface of the flexible substrate. More specifically, an interposer may include one or more lead-like structures formed on a surface of the interposer, the leads being deflectable so as to be positionable onto bonding pads on a chip, the dam comprising a lead-like structure on the surface of the interposer using the same type of process as used to form actual leads. The dam may have a surface area oriented substantially perpendicular to leads in the interconnection region. The dam may function to block a flow path in conjunction with a structure on another substrate in a package.
The interposer may include an off-edge array of leads connected to the conductive traces for attaching to a chip with an off-edge array of bonding pads. The interposer may comprise a flexible substrate. The interposer may be a tape substrate used in a TAB bonding process. The interposer may include one or more connectors on the interposer surface, the connectors being connected along a conductive pathway to the interposer leads. The connectors may be solder balls connected along a conductive pathway to the interposer""s inner lead system. The interposer may be a substrate having an attached mid-layer substrate material, such as an elastomer, on the chip-attach surface. The chip/interposer assembly may include an interconnection region of parallel rows of bonding pads and connected leads. The dams may be disposed in between the ends of the parallel rows of bonding pads and connected leads. The invention may be used to package a DRAM memory chip.
These and other features of the present invention are described below in more detail.